Volatile memories such as dynamic random access memory (DRAM) continue to play a major role in modern electronics due to their high integration density and operating speed. These memories are commonly used, for instance, as the main memories, caches, and data buffers of personal computers, workstations, gaming-consoles, and handheld devices, to name but a few.
One major drawback of volatile memories is that their memory cells lose stored data in the absence of applied power. This data loss typically occurs because stored electrical charges tend to diffuse away from the constituent memory cells, allowing stored data to fade over time. DRAM cells, for instance, store data by placing electrical charge on capacitors, and the stored information fades as the charge dissipates or leaks away from the capacitors.
To prevent stored information from being lost entirely, volatile memory cells may be periodically refreshed (or recharged) during a refresh operation. A typical refresh operation comprises a sensing step for detecting the logic state (e.g., ‘0’ or ‘1’) of stored data, and a refresh step for applying additional charge to the cells in accordance with the detected logic state.
Unfortunately, different volatile memory cells tend to have different charge retention characteristics due to variances in memory fabrication processes. As a result, some memory cells may need to be recharged more frequently than others. In other words, due to the different charge retention characteristics, some memory cells lose data more quickly than other memory cells and require the application of a refresh operation having a shorter period.
The presence of memory cells with different refresh requirements creates a number of potential problems for the overall design and timing of volatile memory devices. For instance, if all memory cells are required to be refreshed with the same period, the period must be short enough so that data is not lost from the memory cells having the poorest charge retention characteristics. This, however, results in inefficient power consumption. On the other hand, if different refresh timing is used for different memory cells, the memory device may require complex additional circuitry and logic, resulting in inefficient use of chip area.
In sum, there is a tradeoff between the specificity of refresh timing and the complexity of refresh circuitry. As refresh timing becomes more specific to the requirements of individual memory cells, the complexity of refresh circuitry tends to increase, and vice versa.